Embedded Capacitance Material - FaradFlex™
Copper Foil Division

Embedded Capacitance Material - FaradFlex™

High-performance materials for embedded capacitors, supporting improved electrical performance and higher circuit integration.

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summary

A thin, high-capacitance dielectric layer is integrated between two copper foils to form a compact embedded capacitance structure.

  • Schematic diagram of noise suppression using conventional external chip capacitors. This image visually explains the factor (parasitic inductance) that makes it difficult to suppress noise at high frequencies due to long wiring because of the physical distance from the IC to the capacitor.
  • Wiring image of board-integrated capacitor by FaradFlex™. . Schematic diagram of the structure that achieves efficient power supply and noise reduction by placing a thin-film insulating layer directly under the IC.
  • Plane resonance simulation data for FaradFlex™. installation study. This graph visualizes the resonant noise in the board generated in a specific frequency band (mainly above 300 MHz) and is used to check the noise level before countermeasures are taken.
  • Data for comparison with FaradFlex™. (second image). The graph shows that while noise was kept below -20dB when FaradFlex™. was used, the chip capacitor-only configuration showed a significant noise deterioration with voltage turning positive (up to +7dB) at certain frequencies.
  • The sandwich structure of an insulator sandwiched between conductors is visualized. Upper layer: copper foil (18 to 70 µm) Middle layer: dielectric layer (3 to 25 µm)A white particulate pattern on a yellow background. Lower layer: Copper foil (18 to 70 μm)

  • Product Images: Substrate-embedded Capacitor Materials

  • Schematic diagram of noise suppression using conventional external chip capacitors. This image visually explains the factor (parasitic inductance) that makes it difficult to suppress noise at high frequencies due to long wiring because of the physical distance from the IC to the capacitor.

    Conventional wiring image

  • Wiring image of board-integrated capacitor by FaradFlex™. . Schematic diagram of the structure that achieves efficient power supply and noise reduction by placing a thin-film insulating layer directly under the IC.

    Wiring image using FaradFlex™. .

  • Plane resonance simulation data for FaradFlex™. installation study. This graph visualizes the resonant noise in the board generated in a specific frequency band (mainly above 300 MHz) and is used to check the noise level before countermeasures are taken.

    Noise reduction simulation_FaradFlex™. .

  • Data for comparison with FaradFlex™. (second image). The graph shows that while noise was kept below -20dB when FaradFlex™. was used, the chip capacitor-only configuration showed a significant noise deterioration with voltage turning positive (up to +7dB) at certain frequencies.

    Noise reduction simulation_Chip capacitor

  • The sandwich structure of an insulator sandwiched between conductors is visualized. Upper layer: copper foil (18 to 70 µm) Middle layer: dielectric layer (3 to 25 µm)A white particulate pattern on a yellow background. Lower layer: Copper foil (18 to 70 μm)

    Substrate-embedded capacitor materials

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FaradFlex™ is an embedded capacitor material designed for high-performance networking and computing applications, including switches, routers, servers, high-layer-count substrates, and MEMS microphones. By stabilizing the power supply, FaradFlex™ enhances signal integrity and overall system performance. It also reduces the number of discrete components on the board, enabling lower communication noise, thinner and more compact designs, and reduced material consumption.​

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